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Espressif Systems /ESP32-S2 /UART0 /INT_ST

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Interpret as INT_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXFIFO_FULL_INT_ST)RXFIFO_FULL_INT_ST 0 (TXFIFO_EMPTY_INT_ST)TXFIFO_EMPTY_INT_ST 0 (PARITY_ERR_INT_ST)PARITY_ERR_INT_ST 0 (FRM_ERR_INT_ST)FRM_ERR_INT_ST 0 (RXFIFO_OVF_INT_ST)RXFIFO_OVF_INT_ST 0 (DSR_CHG_INT_ST)DSR_CHG_INT_ST 0 (CTS_CHG_INT_ST)CTS_CHG_INT_ST 0 (BRK_DET_INT_ST)BRK_DET_INT_ST 0 (RXFIFO_TOUT_INT_ST)RXFIFO_TOUT_INT_ST 0 (SW_XON_INT_ST)SW_XON_INT_ST 0 (SW_XOFF_INT_ST)SW_XOFF_INT_ST 0 (GLITCH_DET_INT_ST)GLITCH_DET_INT_ST 0 (TX_BRK_DONE_INT_ST)TX_BRK_DONE_INT_ST 0 (TX_BRK_IDLE_DONE_INT_ST)TX_BRK_IDLE_DONE_INT_ST 0 (TX_DONE_INT_ST)TX_DONE_INT_ST 0 (RS485_PARITY_ERR_INT_ST)RS485_PARITY_ERR_INT_ST 0 (RS485_FRM_ERR_INT_ST)RS485_FRM_ERR_INT_ST 0 (RS485_CLASH_INT_ST)RS485_CLASH_INT_ST 0 (AT_CMD_CHAR_DET_INT_ST)AT_CMD_CHAR_DET_INT_ST 0 (WAKEUP_INT_ST)WAKEUP_INT_ST

Description

Masked interrupt status

Fields

RXFIFO_FULL_INT_ST

This is the status bit for UART_RXFIFO_FULL_INT when UART_RXFIFO_FULL_INT_ENA is set to 1.
TXFIFO_EMPTY_INT_ST

This is the status bit for UART_TXFIFO_EMPTY_INT when UART_TXFIFO_EMPTY_INT_ENA is set to 1.
PARITY_ERR_INT_ST

This is the status bit for UART_PARITY_ERR_INT when UART_PARITY_ERR_INT_ENA is set to 1.
FRM_ERR_INT_ST

This is the status bit for UART_FRM_ERR_INT when UART_FRM_ERR_INT_ENA is set to 1.
RXFIFO_OVF_INT_ST

This is the status bit for UART_RXFIFO_OVF_INT when UART_RXFIFO_OVF_INT_ENA is set to 1.
DSR_CHG_INT_ST

This is the status bit for UART_DSR_CHG_INT when UART_DSR_CHG_INT_ENA is set to 1.
CTS_CHG_INT_ST

This is the status bit for UART_CTS_CHG_INT when UART_CTS_CHG_INT_ENA is set to 1.
BRK_DET_INT_ST

This is the status bit for UART_BRK_DET_INT when UART_BRK_DET_INT_ENA is set to 1.
RXFIFO_TOUT_INT_ST

This is the status bit for UART_RXFIFO_TOUT_INT when UART_RXFIFO_TOUT_INT_ENA is set to 1.
SW_XON_INT_ST

This is the status bit for UART_SW_XON_INT when UART_SW_XON_INT_ENA is set to 1.
SW_XOFF_INT_ST

This is the status bit for UART_SW_XOFF_INT when UART_SW_XOFF_INT_ENA is set to 1.
GLITCH_DET_INT_ST

This is the status bit for UART_GLITCH_DET_INT when UART_GLITCH_DET_INT_ENA is set to 1.
TX_BRK_DONE_INT_ST

This is the status bit for UART_TX_BRK_DONE_INT when UART_TX_BRK_DONE_INT_ENA is set to 1.
TX_BRK_IDLE_DONE_INT_ST

This is the status bit for UART_TX_BRK_IDLE_DONE_INT when UART_TX_BRK_IDLE_DONE_INT_ENA is set to 1.
TX_DONE_INT_ST

This is the status bit for UART_TX_DONE_INT when UART_TX_DONE_INT_ENA is set to 1.
RS485_PARITY_ERR_INT_ST

This is the status bit for UART_RS485_PARITY_ERR_INT when UART_RS485_PARITY_INT_ENA is set to 1.
RS485_FRM_ERR_INT_ST

This is the status bit for UART_RS485_FRM_ERR_INT when UART_RS485_FRM_ERR_INT_ENA is set to 1.
RS485_CLASH_INT_ST

This is the status bit for UART_RS485_CLASH_INT when UART_RS485_CLASH_INT_ENA is set to 1.
AT_CMD_CHAR_DET_INT_ST

This is the status bit for UART_AT_CMD_CHAR_DET_INT when UART_AT_CMD_CHAR_DET_INT_ENA is set to 1.
WAKEUP_INT_ST

This is the status bit for UART_WAKEUP_INT when UART_WAKEUP_INT_ENA is set to 1.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd